High-speed data communication is a prominent factor in computer systems. There has been a need of a higher-bandwidth, faster-speed interconnect technology for computer systems and peripherals. The Peripheral Component Interconnect (PCI) Express (PCIe) interface protocol is quickly becoming a widely used standard across the computer industry for a high-speed data communication link. The production flow of PCIe devices often involves a testing procedure that is conducted on a production line in a manufacturing facility. As a result, there has also been a need for optimizing such a testing procedure to reduce the testing time that is required to maintain a high yield for the production line and thus reduce manufacturing costs.
Conventionally, when multiple PCIe devices need to be tested, a PCIe tester is required to test one PCIe device at a time. A testing procedure of a PCIe device usually involves inserting the PCIe device under the test (DUT) into a selected PCIe slot on a CPU server platform, turning on the server's power to scan and recognize the PCIe device and then allocate and configure hardware resources (memory, interrupts, etc.) to work with the identified device, installing a low level device driver to enable the software application program interface (API) to call the PCIe device, and running a test program to execute test routines targeting the PCIe device. However, after running the test program, the PCIe tester is required to power off the server, unplug the tested PCIe device, and prepare the second PCIe device to be tested.
Accordingly, each of these steps is time consuming and increases manufacturing costs due to hardware and/or software limitations. As such, what is needed to overcome the described shortcomings is a time-efficient method for testing one or more PCIe devices concurrently.